1. Technical Field
The present invention relates to a semiconductor device.
2. Description of the Related Art
In the related art, there is a wiring conductor layer where an adhesive metal layer, a first diffusion preventing layer, a main conductor layer made of Au, a second diffusion preventing layer made of Pt, a Sn layer, and a brazing filler metal layer made of Au-M (M is Sn, Si, or Ge) alloy are sequentially formed on an upper surface of an insulation substrate (see JP-A-2002-124524, for example).
Incidentally, when connecting substrates having different linear expansion coefficients to each other using an Au—Sn alloy, that is an alloy of gold (Au) and tin (Sn), and in a case where a stress is generated between the substrates by heating or heat generation, there are some cases that connection portions of the substrates are damaged.
In addition, there is a possibility that such damage similarly occurs in the connection portions in a case where a substrate and an element having different linear expansion coefficients and elements are connected to each other using an Au—Sn alloy, or in the connection portions in a case where elements having different linear expansion coefficients are connected to each other using an Au—Sn alloy.
Such damage to the connection portions, as described above, occurs as Au—Sn alloy has a very high hardness and the stress generated between the substrates is not absorbed. In addition, if the damage to the connection portion occurs, reliability of a device entirely decreases. Such a decrease in reliability similarly occurs in a semiconductor device as well.